e014010.PDF

GENERAL INTEREST

PCI Bus Prototyping

Card (2)

developments from ISA to PCI

By B.Kluth and C.Kluth (B&C Kluth GbR)

Ever since IBM-compatible PCs have been available, a new bus system

has been introduced each time there was a major development step. The

PCI bus, which represents the current state of affairs, is not limited to

IBM-compatible computers and should survive for several PC genera-

tions, thanks to its high level of performance. The price for this is a rela-

tively complex structure, which is thoroughly described in this article.

Elektor Electronics

4/2001

GENERAL INTEREST

PCI bus characteristics

In 1985, IBM unveiled the ﬁrst AT

computer. The bus system used at

that time was the ISA bus. Shortly

after this introduction, however, it

quickly became evident that the ISA

bus no longer represented the current

state of technical development. It

was clear that ’286 processors were

already being slowed down by the

bus, for example when working with

graphics cards or high-speed network

technologies. This large loss in per-

formance was due to backwards

compatibility with older 8-bit sys-

tems. The rather low bus clock rate of

6 MHz, which was later increased to

8 MHz, also did not help matters. The

result was a theoretical data transfer

rate of 8 MB/s with a bus width of 16

bits. In actual practice, however, the

maximum achievable data rate was

around 4 to 6 MB/s.

somewhat nervous market, sought

a bus system that was inexpensive

but still capable of high perfor-

mance. After a few false starts, this

resulted in the VLB bus (VESA

Local Bus). It also had a bus width

of 32 bits and a clock rate of 25 to

60 MHz. Various versions of this

bus appeared, namely VLB-1.0

(clock rate 25–40 MHz), VLB-2.0

(clock rate 25–50 MHz) and VLB-

64 bit (clock rate 25–60 MHz). The

main problem with this bus tech-

nology was non-conformance with

the various specifications. The

VLB-1.0 specification allowed only

two slots to be used up to a maxi-

mum CPU clock rate of 40 MHz.

However, some manufacturers built

systems with up to three slots at a

50 MHz clock rate. This resulted in

significant problems with the sta-

bility of individual systems.

The PCI bus consists of three distinct mod-

ules:

–

the Data Path Unit,

–

the Expansion Bus Interface,

–

the Host Bridge, with a cache DRAM con-

troller.

The Data Path Unit is used to set up a 32-bit

link to the individual components in the sys-

tem. Other bus systems can be connected

via the Expansion Bus Interface (e.g. ISA or

AGP). The Expansion Bus Interface and addi-

tional system bridges provide for upwards

compatibility with the ISA bus system, for

example, or new technologies such as AMR.

The Host Bridge is the central component of

the PCI bus system. It can be used to create a

link between the PCI bus and the CPU. In

addition, it converts PCI cycles into CPU

cycles and vice versa. It makes the PCI bus

processor-independent, in contrast to other

bus systems, since all that is necessary to

connect the PCI bus to a particular processor

type (Intel, Alpha, AMD etc.) is to use a dif-

ferent Host Bridge. This characteristic makes

the PCI bus system relatively independent of

future processor generations, as well as

extensible.

The MCA bus

The PCI bus

This problem was the incentive for

IBM to develop a new bus system

suitable for 32-bit operation. In 1987,

the Micro Channel Architecture

(MCA) was introduced into the mar-

ket. This system had a 32-bit data

and address bus with multi-master

capability, and it promised data

transfer rates of up to 16 MB/s.

Unfortunately, the new computers

did not come with any old-style ISA

slots, and consequently this bus was

not a commercial success.

The initial design of the Peripheral

Component Interface (PCI) bus was

made by Intel in 1991. The main rea-

sons for the development of this new

bus were:

The PCI speciﬁcation

–

to achieve higher data rates than

with the 16-bit ISA bus,

The PCI specification allows a total of ten

devices on a PCI bus. Since the Host Bridge

is seen as a PCI device by the PCI bus, there

is basically provision for only nine devices.

These can be used for on-board components

(SCSI, EIDE, LAN and so on) or for PCI slots

for connecting PCI cards. In this regard, you

must bear in mind that each slot demands

two devices, so that at most four slots can be

driven by a PCI bus. However, the number of

slots can be increased by connecting a sec-

ond PCI bus system to the Expansion Bus

Interface. In total, up to 256 busses can be

strung together, with the first 255 busses

being PCI busses and the final bus allowed

to be an ISA, EISA or VL bus, or even an MCA

bus. Large systems can be implemented in

this manner (see Figure 1 ).

Another option for slot extension can be seen

on current motherboards (such as the Abit

KT-7, Gigabyte ZX and Epox EP-8KTA+). Here

up to six slots are driven on one motherboard

by means of IRQ sharing. In this scheme,

slots 5 and 6 (for example) share an IRQ.

However, if more than four PCI cards are

used, performance suffers. Also, it is not pos-

sible to guarantee in principle that all possible

PCI card combinations will function without

any problems.

–

to achieve better electromagnetic

compatibility (EMC) than with

previous systems,

–

to achieve an assured future with

following processor generations.

The EISA bus

In 1992, the design was complete

and the first PCI bus was unveiled.

In the course of subsequent devel-

opment of this bus system, various

specifications arose (versions 1.0,

2.0, 2.1 and 2.2, which is the current

version). The result of the demand-

ing requirements defined in 1991 is

a 32-bit bus system that transfers

data and addresses in a time-multi-

plexed manner and that can execute

variable-length burst cycles. Intel

was able to win acceptance for a

complete, realistic and well-struc-

tured set of definitions of all impor-

tant bus signals as the basis for the

PCI bus. One objective in the devel-

opment of this hierarchical,

upwardly open bus system was to

avoid repeating the mistakes that

were made with the previous bus

systems .

The experience with the failed MCA

bus played a major role in the devel-

opment of the Extended Industry

Standard Architecture (EISA) bus.

The EISA bus works with an 8-MHz

clock and 32-bit technology. With a

bus width of 32 bits, the resulting

data transfer rate is 16 MB/s in stan-

dard mode and 32 MB/s in burst

mode. Later on, two other burst

modes were added (EMB-66 and

EMB-133), which allowed data rates

of up to 133 MB/s. However, this

level of performance had its price, so

it was only used in expensive server

systems.

The VLB bus

Various manufacturers of peripheral

equipment, along with a now

4/2001

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GENERAL INTEREST

A wide variety of PCI cards can be connected

via the slots. The following types of cards are

distinguished:

–

Host Subsystem with Host Bridge

single-function PCI cards,

–

multi-function PCI cards,

PCI Bus (primary)

–

multi-device PCI cards.

Single-function cards can for example be

graphics cards or SCSI host cards. A PCI

device can have up to eight different I/O func-

tions, which yields the multi-function PCI

cards. A multi-device PCI card can consist of

several of the above-mentioned types of PCI

cards. With a multi-device card, a wide vari-

ety of devices can be connected via a PCI-to-

PCI bridge. This means that a multi-device

PCI card represents a complete PCI bus sys-

tem.

PCI

Device

(LAN)

PCI

Device

(EIDE)

PCI

Device

(VGA)

PCI-to-PCI

Bridge

PCI Bus (secondary)

PCI-to-

XXX

Bridge

PCI

Device

(SCSI)

PCI

Device

(TV)

PCI

Device

(LAN)

Plug-and-Play function (PnP)

Standard I/O Bus (XXX: EISA/ISA/PCI/MCA)

With regard to the PCI bus, Plug-and-Play

means the following:

After the computer is switched on, the BIOS

ﬁnds all PCI devices and queries each device

for the resources that it needs. The necessary

resources usually consist of I/O addresses,

IRQ numbers, DMA channels and memory

regions used by the device. If there are over-

laps in the resources needed by two different

cards, the BIOS attempts to enable both cards

to work in the system by reconﬁguring one of

the cards. If this cannot be done, the BIOS

simply disables one of the two cards. How-

ever, this happens only very rarely. The

resources used by each PCI card are made

available to the operating system being used

via the ESCD database of the BIOS. Further-

more, this information is also stored in the

Conﬁguration Space of the PCI card, which is

a memory region of up to 256 bytes (see

Table 1 ). The BIOS has also obtained infor-

mation about the necessary resources from

this memory region, and it makes this infor-

mation available to other applications via

special BIOS interrupt calls. Since these BIOS-

specific parameter registers are managed

dynamically in each system, there is not any

standardised, ﬁxed memory location (such as

a MEM address) speciﬁed for them. The only

Standard I/O Bus Device

010015 - 11

Figure 1. The hierarchical structure of the PCI bus system.

way to obtain this information is to

use a software interrupt, which is

prescribed for all motherboard man-

ufacturers.

Using Status and Command , it is

possible to read out information

regarding the cards being used, and

in some cases to modify the settings.

The Vendor ID is the number of the

manufacturer of the card being used.

This number is assigned by the PCI

SIG (PCI Special Interest Group). The

PCI SIG is a consortium that super-

vises all specifications for the PCI

bus. The official PCI bus specifica-

tions, which contain detailed expla-

nations of the registers, can also be

obtained via this organisation.

PCI devices can be divided into two

groups, called Initiators (masters)

and Targets (slaves). An Initiator

causes a data transfer to take place

by assuming control of the control

signals and specifying the details of

the data transfer (addresses, start,

etc.). A Target generates a hand-

shake signal for the Initiator after it

recognises its address on the PCI

bus (initialisation phase). In addi-

tion, it can indicate whether data are

available or whether it is ready to

receive data, and it can signal a

request for wait cycles. The collec-

tive functions of a PCI bus system

can be utilised by employing these

two groups.

However, it is possible for all PCI

devices on a bus to represent PCI

bus masters. In this case, the arbi-

tration logic must decide which mas-

CLK

Address 1

Data 1

Data 2

Data 3

010015 - 12

Figure 2. Burst mode timing.

Elektor Electronics

4/2001

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ter is allowed to use the PCI bus

(arbitration phase). During this

phase, the two PCI devices must

determine which mode will be used

for the data transfer: burst mode or

non-burst mode. Burst mode ( Fig-

ure 2 ) is normally used to transfer

four or more DWORDs (a double

word is 32 bits of data), with the

address being sent ﬁrst, followed by

the associated data. In non-burst

mode ( Figure 3 ), a DWORD address

is sent before each DWORD. This

leads to different data rates for the

two modes. In non-burst mode, the

resulting data rate is 44 MB/s for

reading (3 cycles per DWORD) and

66 MB/s for writing (2 cycles per

DWORD). Since one cycle is needed

for each subsequent DWORD in

burst mode, the data rate

approaches 117 MB/s as the burst

length (number of DWORDs)

increases. With the PCI Bus 2.1

specification (32-bit PCI bus at

33 MHz), data transfer rates of up to

117 MB/s can be achieved. The PCI

Bus 32-bit 2.1 specification (32-bit

PCI bus at 66 MHz) allows for data

transfer rates up to 234 MB/s, and in

the PCI Bus 64-bit 2.1 specification

(64-bit PCI bus at 66 MHz), the max-

imum data transfer rate can be as

high as 468 MB/s (see Table 2 ).

Table 1 PCI card Configuration Space

Device ID

Vendor ID

00h

Status

Command

04h

Class Code

Revision ID

08h

BIST

Header Type

Latency Timer

Cache Line Size

0Ch

Base Address 0

10h

Base Address 1

14h

Base Address 2

18h

Base Address 3

1Ch

Base Address 4

20h

Base Address 5

24h

Cardbus CIS-Pointer

28h

Subsystem ID

Subsystem Vendor ID

2Ch

Expansion ROM Base Address

30h

Reserved

34h

Reserved

38h

Max_Lat

Min_Gnt

Interrupt Pin

Interrupt Line

3Ch

Cycle 2:

FRAME# is activated by the master

device to indicate the start of a

transaction.

AD holds an address.

C/BE# holds a bus command.

IRDY#, TRDY# und DEVSEL# are in

a turn-around cycle, since a driver

changeover occurs.

has recognised the address from Cycle 2.

Cycle 5:

AD still holds the ﬁrst data from data phase 1.

TRDY# is inactive, since the target (data

source) wants to insert a pause.

Cycle 6:

AD holds the data from data phase 2.

TRDY# indicates that the data can be read.

PCI bus timing

Cycle 3:

AD performs a turn-around, since

control passes from the master to the

target.

C/BE# is driven by Byte Enable.

IRDY# is active, because the master

is ready to read the data.

TRDY# remains inactive, since no

target has been found yet.

Cycle 7:

AD carries the data for data phase 3.

IRDY# is deactivated by the master, since it

wants to have a wait state.

PCI is a synchronous bus, which

sends and receives all data transfers

with reference to a system clock

(CLK) signal. The mutual relation-

ships of the individual signals can be

illustrated using the Read command

as an example (see also the timing

diagram shown in Figure 4 ). The

individual steps in processing a

Read command are the following:

Cycle 8:

FRAME# is deactivated by the master, since

the ﬁnal data block will now be transferred.

Cycle 4:

AD holds the ﬁrst data.

TRDY# is active, since the ﬁrst read-

able data are on the bus.

DEVSEL# is active, since the target

Cycle 9:

FRAME#, AD and C/BE# initiate turn-

arounds, so the drivers can change over.

IRDY#, TRDY# and DEVSEL# are inactive,

since no transaction is taking place.

Cycle 1:

The PCI bus is in the idle state.

CLK

Address 1

Data 1

Address 2

Data 2

010015 - 13

Figure 3. Non-burst-mode timing.

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GENERAL INTEREST

The bus is in the idle state, since

FRAME# = 1 and IRDY# = 1.

Table 2 The various PCI specifications and associated data transfer rates

32 Bit 1.0

64 Bit 2.0

32 Bit 2.1

64 Bit 2.1

PCI-Bus

Figure 5 shows an overview of the

individual signal lines.

Bus type

synchronous

Clock rate, MHz

PCI speed

with slots

Data bus width, bits

Thanks to its independence from the

speed of the processor, the PCI bus

can offer new possibilities for appli-

cations such as multimedia, net-

working, instrumentation and many

others. This is primarily due to its

very high data transfer rates (espe-

cially the PCI Bus 64-bit 2.1 version),

which allow data to be processed

faster between PCI cards and the

processor, in both directions. If you

use an ‘old’ ISA sound card in com-

bination with a PCI 3-D graphics

accelerator card, you could be slow-

ing down your system by up to

10–20% under certain conditions if

the available performance of the PCI

card is fully exploited.

The individual BIOS settings of the

computer are also important with

regard to stable system perfor-

mance, since they have considerable

inﬂuence on system stability. Thanks

to the wide data bus and high clock

rates of modern motherboards, the

PCI bus works at higher speeds than

the standard ISA bus, for example.

For error-free data traffic, it is there-

fore often necessary to delay the PCI

bus, since the motherboard cannot

always match the limits of the hard-

ware plugged into the slots. The fol-

lowing options adjust the length of

the delay on the PCI bus for a trans-

action between the specified PCI

slot and the CPU. The value depends

on the PCI master unit that is used,

among other things.

One of the most important settings

is the time value of the PCI Latency

Timer, which normally should be set

to 32 clock cycles. This option deter-

mines how long a PCI card is

allowed to reserve the PCI bus as a

bus master when another PCI card

has also requested access to the

bus. If the setting for the duration of

the PCI Latency Timer is too short or

too long, it may be possible for the

CPU to access the hardware faster

than is permitted by the processing

in the decoder. Although this can

handsomely boost the speed of both

the computer and the cards (espe-

Address bus width, bits

Number of devices

Number of slots

Max. burst length

unlimited

Data rate at 33 MHz with no extra wait cycles, MB/s

Non-Burst-Read

Non-Burst-Write

132

Burst-Read

106

211

106

211

Burst-Write

117

234

117

234

Data rate at 66 MHz with no extra wait cycles, MB/s

Non-Burst-Read

172

Non-Burst-Write

132

264

Burst-Read

211

423

Burst-Write

234

468

Autoconfiguration

yes

Concurrency

yes

Interrupt Sharing

yes

CLK

Address 1

Data 1

Data 2

Data 3

FRAME

C/BE

Bus-Cmd

BE's

IRDY

TRDY

DEVSEL

Address

Phase

Data

Phase

Data

Phase

Data

Phase

Bus Transaction

010015 - 15

Figure 4. PCI timing diagram for the Read command.

Elektor Electronics

4/2001

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