volume37-number3(1).pdf
(
1297 KB
)
Pobierz
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
A forum for the exchange of circuits, systems, and software for real-world signal processing
1
781
329 4
700
Volume 37, Number 3, 2003
Editor’s Notes
2
A Reader Notes
2
How to Save Power in Battery Applications
Using the Power-Down Mode in an ADC
3
Advanced Digital Post-Processing Techniques Enhance
Performance in Time-Interleaved ADC Systems
5
Dynamic Memory Allocation Optimizes
Integration of Blackfin® Processor Software
10
Product Introductions
15
Authors
15
Editor’s Notes
RF IS EVERYWHERE—BEWARE!
It’s high time for a reminder of a theme
that cannot be repeated too often: the
need for designers of precision low level
dc and low frequency equipment to be
alert to the adverse effects of ever-
increasing ambient high frequency
radio-frequency energy, from MHz to
GHz, on their measurements. In this
world, conductors form antennas,
converting electromagnetic waves into voltages and currents—
both normal-mode and common-mode. Shielding and iltering
are ine, but how many op amp data sheets ordinarily specify CMR
at radio frequencies?
We have published warnings. For example, in “Ask the
Applications Engineer—14,” there is a discussion of high
frequency signal contamination,
1
and in a later issue, further
illumination of the subject by a reader.
2
Walt Jung’s recent book,
Op Amp Applications
, contains substantive discussions—including
a useful set of references—in a 30-page section headed “EMI/RFI
considerations.”
3
You can ind an earlier version of this section
online in the Hardware Design chapter of the
online
seminar book,
Practical Analog Design Techniques
, edited by Walt Kester.
4
Also,
in 1996 (Volume 30, No. 2), we published “A Bibliography on
EMC/EMI/ESD,” by Daryl Gerke, P.E., and William Kimmel,
P.E.,
5
describing a variety of useful texts on these topics.
In
Analog Dialogue
online, 35-4, August 2001, we published an
item by a reader, Herman R. Gelbach, P.E., “A Reader Notes,”
stressing the problem of common-mode RFI. This note has
never appeared in print, but it deserves preservation (and our
readers need the information), so it is revived below in (relatively)
indestructible print.
device to the impressed signal. I am led to assume that he has
never checked for high-frequency common-mode voltages, but
a couple of years ago at a seminar that I conducted for the local
IES chapter, I checked!
I found in an after-working-hours ofice environment, on the end
of a 50-foot water-pipe-grounded input lead a couple of hundred
millivolts of high-frequency CM trash. This will give
signiicant
offset (slewing) errors in
any
unprotected instrumentation
ampliier that I have ever tested—and that’s dozens of different
commercial instrument designs. See Figure 3 of my paper for a
real-life
clean
laboratory environment. It shows about 400 mV
p-p of high-frequency trash. Most important, no grounding
scheme—except a continuous sheet of copper with
all
system
components, including signal wiring and sensors intimately in
contact with it—will get rid of this! Maxwell’s and Heaviside’s
equations still are with us. The only practical solution is to
prevent the unwanted high-frequency signals from reaching
the point of rectiication.
A similar comment would apply to Albert O’Grady’s article.
8
High-frequency CM is ever present in measurement systems,
especially in these days of computers and RF-coupled telephones.
Even the design of the remote-sensing transducer excitation-
supply error ampliier must consider this error source! On page
37, he talks of parasitic thermocouples and how to eliminate the
effect. Unfortunately, such offsets are likely to be insigniicant
relative to offsets caused by RF induced in the system’s wiring.
The application of the suggested process only contributes more
unknown errors. Gold-copper and copper-copper thermocouples
have an extremely low output, so the source of the errant emf is
not thermoelectric if normal care is used in the system design.
A test that I had run many years ago tested the variation in voltage
at an ampliier input from a loop consisting of signal-conditioner
board-edge connector, AMP patchboard connectors, balance pit
patch board Deutsch connectors, in-model Winchester SMRE
connectors, and was terminated in the two wires being connected
to the two terminals of a Constantan strain gage glued to the model
structure. Copper-Constantan thermocouples have a very high
output; therefore an output might be expected if the temperature
of the couples was not exactly matched. The total loop length was
perhaps 200 ft.
The loop voltage was observed with an Astrodata Nanovoltmeter,
easily capable of 100-nanovolt stability over the test time. The
observed loop-voltage variation over the 8-hour shift was
3 microvolts, p-p. This included wind-tunnel warmup and
several Mach series from 0.3 to 0.95 Mach. Balance pit and model
temperatures, with the several connectors, varied to 130F. In
another test of a few Dynamics, Inc., ampliiers, they were found
to repeat offsets within 1/8 microvolt RTI over a week’s time using
the normal system calibration relays and resistance dividers.
These
are raw data without any modiication
. The ampliiers have PMI/ADI
MAT01 matched monolithic dual-transistor input pairs. Because
of the results of the two cited tests, I am completely unimpressed
with discussions of correcting for thermal offsets in wiring.
If any of your readers (or colleagues) are interested in my
comments, and can’t ind a copy of the above-mentioned ISA
paper, or if they have an interest in a writeup that I made for
Scanivalve Co.,
9
“What do I do with this third wire?” please
email me. The latter article should be required reading for any
one interested in the subject of “grounding” and shielding of
sensors, and their interconnection to the receiving device and
its “ground.”
–
Dan Sheingold,
Editor
A READER NOTES:
[From
Analog Dialogue
35-4, August 2001. www.analog.com/library/
analogDialogue/archives/35-04/reader.html]
High-Frequency-Caused Errors in Millivolt-Measurement Systems
By Herman R. Gelbach, P.E. ret. (hrgelbach@juno.com)
[Editor’s Note: Herman never tires of reminding us of the effects of EMI
in precision data systems. Faithful readers may recall the adventure that
he and our James Bryant shared, summarized in an article that was
included in our “Ask The Applications Engineer” collection.
1
In the
present communication, he takes us to task with respect to a couple of
recent Analog Dialogue articles, for not once again reminding designers
who use precision ICs that they must deal with both normal-mode and
common-mode threats to instrumentation-system accuracy. Herman is
a Life Fellow of the Instrument Society of America (ISA) and is a design
consultant to Scanivalve Co. If you wish to see any of his writings on this
subject, get in touch with him at the above email address.]
I am saddened that the many copies of my ISA paper,
6
High-
Frequency Common Mode, The Contaminator of Signals
, which have
been sent to ADI are apparently gathering dust. Scott Wayne
states “all Analog Devices instrumentation ampliiers are fully
speciied for both dc and low-frequency ac common mode
rejection.”
7
He has completely missed mentioning the source
of high-frequency induced errors, unequal slewing of the input
(continued on page 14)
ISSN 0161-3626 ©Analog Devices, Inc. 2003
2
Analog Dialogue Volume 37 Number 3
How to Save Power in Battery
Applications Using the Power-Down
Mode in an ADC
By Mercedes Casamayor
[mercedes.casamayor@analog.com]
Claire Croke [claire.croke@analog.com]
Size and power consumption are two critical features in portable
battery-powered applications. Otherwise acceptable components
can be designed out of portable systems based on deiciencies in
these two features alone. Everybody desires smaller, more compact
mobile phones, MP3 players, PDAs, and digital cameras—with
increased time between battery charges or replacement. For
semiconductor manufacturers, this translates into a requirement
for lower power ICs with high performance and the same—or even
extra—features in ever smaller packages.
In portable battery-powered applications, battery life is a critical
concern to the system designer. Battery discharge curves differ,
depending on the type of battery and the current drain. For
example, Figure 1 shows the typical discharge curves for a
Lithium/MnO
2
(primary) cell with three typical current loads.
They show that the higher the current it must supply, the shorter
the battery’s life. Since even small amounts of current shorten the
battery’s life, minimizing the current drawn quiescently by the
system components when not operating—or whenever possible
during operation—can extend battery life.
Nowadays, almost every analog/digital converter (ADC) sold
into the battery-powered device market provides a power-down
mode as a standard feature. The technique used to place the
ADC into the power-down state—and its effectiveness—differ
from part to part.
Some ADCs have a dedicated shut-down pin to shift the device
into power-down mode. The weakness of this approach is that an
extra pin, which results in increased pin count for the ADC, can
increase the package size. Other ADCs, like the AD7887, require
a
write
to an on-board control register to produce a power-down
state. This is generally the case with multichannel ADCs, where
an internal register is used for channel selection as well as mode
selection. This on-board register also means an extra DATA IN
serial interface pin.
In order to cut down on pin count, some recent ADCs use the
standard interface lines to implement power-down modes; an
example is the 12-bit, 1-MSPS AD7476A, available in the tiny
6-pin SC70 package.
The AD7476A’s 3-wire read-only serial interface not only controls
the conversion process and accesses the conversion result from the
ADC—it is also used to establish the device’s different operating
modes. The mode of operation is selected by controlling the
state of
CS
(
conversion start
) during a conversion. This has the
advantage that the signals required to change modes are standard
serial interface signals.
The serial interface consists of the
CS
, SCLK, and SDATA
lines. A normal conversion requires sixteen serial clock pulses
for completion. The
CS
signal is used to initiate the conversion
and to frame the sixteen serial clocks. After the conversion has
been initiated, the time at which
CS
is pulled
high
will determine
if the AD7476A will enter power-down mode—or, if already in a
power-down mode, whether or not the AD7476A will return to
normal operation. Changing the mode of operation can easily be
done with a standard 8- or 16-pulse SCLK burst from a micro-
controller—or with a framing signal of any length from a DSP.
Figure 2 shows the timing diagram during a normal conversion,
and Figure 3 shows how the power-down mode can be entered
by controlling the
CS
signal. This mode of operation is designed
to provide lexible power management options and to minimize
power dissipation for different application requirements.
To reduce power consumption and maintain battery life, the
AD7476A should be placed into its low power state between
conversions or after a burst of several conversions.
LITHIUM/MnO
2
DISCHARGE CURVE
3.5
3.0
2.5
3mA
1mA
0.5mA
2.0
1.5
1.0
0
100
200
SERVICE HOURS
300
400
Figure 1. Typical discharge curves.
CS
1
16
SCLK
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 2. Serial interface signals in a normal conversion.
CS
1 2
10
16
SCLK
THREE-STATE
SDATA
INVALID DATA
Figure 3. Using the serial interface signals to enter power-down mode.
Analog Dialogue Volume 37 Number 3
3
www.analog.com/library/analogdialogue/archives/37-09/ADC_powerdown.html
More about the AD7476A
The AD7476A is a 12-bit successive approximation (SAR-type)
ADC, operating on a 2.35-V to 5.25-V supply and capable of
throughput rates of up to 1 MSPS. The AD7476A combines
CMOS technology and advanced design techniques to achieve
low power-dissipation at high throughput rates.
The AD7476A’s average power consumption during the cycle time
is determined by the percentage of time it spends in a full power
state (operational), as compared to the interval spent in a low power
state (power down). The greater the time spent in power-down,
the lower the average power consumption.
To achieve the lowest power dissipation with the AD7476A,
the conversion should be run as quickly as possible. Since the
conversion time is determined by the SCLK frequency, the faster
the SCLK frequency, the shorter the conversion time. Thus, the
device can remain in the power-down mode for a longer interval
and will dissipate maximum power for a shorter time.
Figure 4 shows the average power consumption by the AD7476A
for different SCLK frequencies with a ixed throughput rate of
100 kSPS. The ADC is put in the power-down mode after the
conversion is complete, and is powered up by means of a dummy
conversion. As the plot shows, the faster the clock frequency, the
lower the average power consumption.
20
made available the AD7466, a
micropower
, 12-bit SAR-type ADC
housed in a 6-lead SOT-23 package. It can be operated from 1.6 V
to 3.6 V and is capable of throughput rates of up to 200 kSPS.
10
THE PART IS POWERED UP ALL THE TIME
1
PLACING THE PART INTO POWER-DOWN
MODE BETWEEN CONVERSIONS
0.1
V
DD
= 3V,
SCLK = 20MHz
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Figure 5. AD7476A power consumption comparison.
The AD7466 powers up prior to conversion and returns to power-
down mode when the conversion is complete; this eliminates the
need for dummy conversions. In the same way as for the AD7476A,
the AD7466’s conversion time is determined by SCLK, allowing
the conversion time to be reduced by increasing the serial clock
speed, thus providing the same kind of power saving.
Figure 6 shows the AD7466’s power consumption for different
throughput rates, serial clock frequencies, and supplies. The
current consumption in power-down mode is typically 8 nA.
The AD7466 consumes 0.9 mW max when operating at 3 V, and
0.3 mW max for 1.8 V operation at 100 kSPS.
F
SAMPLE
= 100kSPS
18
16
14
12
V
DD
= 5V
10
8
1.4
6
V
DD
= 3V, SCLK = 2.4MHz
4
1.2
V
DD
= 3V
2
1.0
0
0
2
4
6 8 10 12 14 16 18
SCLK FREQUENCY (MHz)
20
0.8
Figure 4. AD7476A power consumption for different
serial clock frequencies.
V
DD
= 3V, SCLK = 3.4MHz
0.6
V
DD
= 1.8V, SCLK = 2.4MHz
Figure 5 shows that for a ixed SCLK frequency of 20 MHz, when
operating the ADC at low throughput rates, the average power
consumed by the ADC is very low. However, as the throughput
rate increases, the average power consumption increases, because
the ADC remains in a power-down state for a shorter period of
time compared to the time in the operating state. The other plot
shows the average power consumed by the ADC when there is no
power-down mode implemented between conversions. Together
they show that—while at lower throughput rates signiicant power
savings can be achieved by placing the ADC into a power-down
state between conversions—increasingly diminished power savings
accrue as the conversion rate increases. For example, at 300 kSPS,
the difference between the two cases is less than 0.5 mW.
A further step in the different power-down modes implemented
through standard serial interface signals is the
automatic
power-
down mode. Following the trend of very low power ADCs for
portable battery-powered applications, Analog Devices has recently
0.4
0.2
V
DD
= 1.8V, SCLK = 3.4MHz
0
0
50
100
150
200
250
THROUGHPUT (kSPS)
Figure 6. AD7466 power consumption vs. throughput
rate for different SCLK and supply voltages.
We have shown that faster SCLK frequencies and longer power-
down modes greatly reduce the average power consumed by the
ADC. These power savings, combined with the space-saving
6-lead 2 mm 2.1 mm SC70 surface-mount package, make
the AD7476A an ideal candidate for portable battery-powered
applications and a very compact alternative to other solutions. And
for extremely low-power-budget applications powered at 3.6 V,
the AD7466 is the ideal solution.
b
4
Analog Dialogue Volume 37 Number 3
Advanced Digital Post-Processing
Techniques Enhance Performance
in Time-Interleaved ADC Systems
interleaving all of the individual channel data outputs in the proper
sequence (e.g., 1, 2, 3, 4, 1, 2, etc.). In a two-converter example,
both ADC channels are clocked at one-half of the overall system’s
sample rate, and they are 180 out of phase with one another.
1
4
3
CHANNEL 1
2
By Mark Looney [mark.looney@analog.com]
1
AIN
DATA 1
ANALOG
INPUT
INTRODUCTION
Time interleaving of multiple analog-to-digital converters by
multiplexing the outputs of (for example) a pair of converters
at a doubled sampling rate is by now a mature concept—irst
introduced by Black and Hodges in 1980.
1, 2
While designing a
7-bit, 4-MHz A/D converter (ADC), they determined that a time-
interleaved solution would require less die area than a comparable
2
n
lash converter design. This new concept proved of great value
in their design, but saving space was not its only beneit. Time
interleaving of ADCs offers a conceptually simple method for
multiplying the sample rate of existing high-performing ADCs,
such as the 14-bit, 105-MSPS AD6645 and the 12-bit, 210-MSPS
AD9430. In many different applications, this concept has been
leveraged to beneit systems that require very high sample rate
analog-to-digital conversion.
While the speed and resolution of standard ADC products have
advanced well beyond 4 MHz and 7 bits, time-interleaved ADC
systems (for good reasons) have not advanced far beyond 8-bit
resolution. Nevertheless, at 8-bit performance levels, this concept
has been widely adopted in the test and measurement industry,
particularly for wideband digital oscilloscopes. That it continues to
make an impact in this market is evidenced by the 20-GSPS, 8-bit
ADC that was recently developed by Agilent Labs
3
and adopted by
the Agilent Technologies Ininiium™ oscilloscope family.
4
Indeed,
time-interleaved ADC systems thrive at the 8-bit level, but they
continue to fall short in applications that require the combination
of high resolution, wide bandwidth, and solid dynamic range.
The primary limiting factor in time-interleaved ADC systems
at 12- and 14-bit levels is the requirement that the channels be
matched. An 8-bit system that provides a dynamic range of 50 dB
can tolerate a gain mismatch of 0.25% and a clock-skew error of
5 ps. This level of accuracy can be achieved by traditional methods,
such as matching physical channel layouts, using common ADC
reference voltages, prescreening devices, and active analog
trimming, but at higher resolutions the requirements are much
tighter. Until now devices employing more innovative matching
techniques have not been commercially available.
This article will outline in detail the matching requirements for
12- and 14-bit time-interleaved ADC systems, discuss the idea
of advanced digital post-processing techniques as an enabling
technology, and introduce a device employing the most promising
solution to date,
Advanced Filter Bank
(AFB™), from V Corp
Technologies, Inc.
5, 6
ENCODE
1
= 0
1
= 0
CHANNEL 2
AIN
DATA 2
ENCODE
2
= 90
2
= 90
ANALOG
INPUT
CHANNEL 3
3
= 180
AIN
DATA 3
ENCODE
4
= 270
3
= 180
CHANNEL 4
MASTER
CLOCK
AIN
DATA 4
ENCODE
DATA
OUT
1
2
3
4
1
4
= 270
Figure 1. Four-channel time-interleaved ADC system.
For simplicity, this article focuses primarily on two-converter
systems, but four-converter systems are discussed when required
to articulate key performance differences. Most of the block
diagrams, mathematical relationships, and solutions will highlight
the two-channel coniguration.
Design Challenge of Time Interleaving
As mentioned, channel-to-channel matching has a direct impact
on the dynamic range performance of a time-interleaved ADC
system. Mismatches between the ADC channels result in dynamic
range degradation that—in an FFT plot—show up as spurious
frequency components called
image spurs
and
offset spurs
. The
image spur(s) associated with time-interleaved ADC systems are
a direct result of gain- and phase mismatches between the ADC
channels. The gain- and phase errors produce error functions
that are orthogonal to one another. Both contribute to the
image-
spur
energy at the same frequency location(s). The
offset spur
is
generated by offset differences between the ADC channels. Unlike
the image spur(s), the offset spurs are not dependent on the input
signal. For a given offset mismatch, the offset spur(s) will always be
at the same level. Extensive studies of the behavior of these spurs
have resulted in several mathematical methods for characterizing
the relationship between channel matching errors and dynamic
range performance.
7, 8
While these methods are thorough and very useful, the “error
voltage” approach used here provides a simple method for
understanding the relationship without requiring a deep study
of complex mathematical derivations. This approach is based on
the same philosophy used in Analog Devices Application Note
AN-501
9
to establish the relationship between aperture jitter and
signal-to-noise (SNR) degradation in ADCs. The
error voltage
is
deined as the
difference between the “expected” sample voltage and
the “actual” sample voltage
. These differences are a result of a large
subset of errors that fall into three basic categories:
gain
(Figure 2),
phase
(Figure 3), and
offset
(Figure 4) mismatches.
Time Interleaving Process Overview
Time interleaving of ADC systems employs the concept of running
m
ADCs at a sample rate that is 1/
m
of the overall system sample
rate. Each channel is clocked at a phase that enables the system as
a whole to sample at equally spaced increments of time, creating
the seamless image of a single A/D converter sampling at full
speed. Figure 1 illustrates the block- and timing diagrams of a
typical four-channel, time-interleaved ADC system. Each of the
four ADC channels runs at one-fourth the system’s sample rate,
spaced at 90 intervals. The inal output data stream is created by
Analog Dialogue Volume 37 Number 3
5
www.analog.com/library/analogdialogue/archives/37-08/post_processing.html
Plik z chomika:
TirNaNog
Inne pliki z tego folderu:
volume1-number3(1).pdf
(7733 KB)
volume1-number2(1).pdf
(3887 KB)
volume10-number2(1).pdf
(3533 KB)
volume10-number1(1).pdf
(3227 KB)
volume1-number1(1).pdf
(1913 KB)
Inne foldery tego chomika:
ACE
AcornUser
AmigaComputing
AmigaFormat
AmigaShopper
Zgłoś jeśli
naruszono regulamin