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BASIC CIRCUITS

Pulse Width Modulator

Using GAL16V8

Design by J. Hesse and R. Lessing

Pulse width modulation (PWM) is a fundamental technique in electron-

ics. It comes as no surprise, therefore, that there are many applications

for this digitally-programmed design.

A Question of Software

The only component in the pulse

width modulator is a programmable

logic device, type GAL16V8. This is

ideal for small digital circuits and is

available cheaply (around £2). Also,

the development environment (the

ABEL compiler) is free, and runs on

an ordinary PC. A ‘digital’ pulse

width modulator has the advantage

over its analogue counterpart that it

A pulse width modulator can form the basis

of many fascinating projects. The speed of a

DC motor, for example, can be smoothly var-

ied from zero to 100%. Connect a power MOS-

FET and you can control model trains, drills,

lamps and many other devices. This design

is particularly interesting because of its dig-

ital control input: operation is governed not

by an analogue voltage, but rather by five

binary inputs which can be connected to a

PLC or a microprocessor.

is practically insensitive to variations

in supply voltage and requires no

components such as potentiometers

which are prone to wear. The clean-

liness of the output signal can be

veriﬁed on an oscilloscope.

Figure 1 shows the arrangement

of logic inside the GAL. Pin num-

bers are shown in small squares.

As can be seen, there are seven

inputs ( a-e , OVER and CLK ), and

a

Q0

I_13

19

2

D

Q

I_17

I_110

I_56

CLK

1

2

3

4

5

6

7

8

9

20

V

b

CC

3

a

b

c

d

e

19

Q0

Q1

Q2

Q3

Q4

I_55

P16V8R

c

18

I_9

4

Q1

I_99

I_128

I_11

18

I_54

D

Q

17

I_16

d

I_10

I_111

I_115

5

16

I_82

e

15

6

I_21

OVER

14

PULSEWIDTH

I_93

OVER

Q2

7

13

Q11

Q10

I_7

I_12

D

Q

17

I_121

I_15

12

I_112

I_108

I_19

GND

10

11

I_91

I_6

000123 - 12

Q10

I_90

I_87

12

I_5

PULSEWIDTH

Q3

I_20

D

Q

16

S

Q

14

I_14

I_96

I_89

I_4

I_114

I_109

I_116

R

I_88

I_18

Q11

I_92

I_127

13

I_61

I_63

Q4

I_120

I_64

D

Q

15

I_119

I_62

I_65

I_113

I_60

CLK

1

000123 - 11

Figure 1. The logic circuit programmed into the GAL. The indicated inputs and outputs can be found on the device pinout.

52

Elektor Electronics

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BASIC CIRCUITS

six outputs ( Q0-Q4, Pulsewidth )

which are brought out to pins, as

well as the internal signals Q10 and

Q11 . Q0-Q4 , although brought out

to pins, are not used in the present

application.

Pulses appearing on the CLK

input are fed to a binary counter,

which increments from 0 to 31. The

counter consists of the logic gates on

the left and five D-type flip-flops. The

result at the output of the flip-flops is

compared with a binary value pre-

sented at the inputs a-e and OVER

(≥32). The comparator, which con-

sists of the group of gates on the

right-hand side of the circuit, drives

the reset input of the final set/reset

ﬂip-ﬂop. The set input is active when

the counter is at zero. So, at the

beginning of the count sequence the

Pulsewidth output is set high, and it

remains high until the programmed

count is reached. Then the output

flip-flop is reset and the output is

low for the rest of the count.

The logic equations for the device

(which are less complicated than

they might appear!) are shown in

Figure 2 . They are written for the

ABEL GAL compiler. The ABEL com-

piler is an elusive piece of software,

but is provided as part of the ispDe-

signEXPERT-Starter package. This

software, which can program PALs

and GALs as well is ispLSI, MACH

and ispGAL logic devices of up to

600 macrocells, is freely download-

able from the Lattice homepage

http://www.latticesemi.com .

However, authorisation is

required before the relevant files

(more than 55 MB, plus manuals and

tutorials) can be downloaded from

http://www.latticesemi.com/lit/html/

starter/ispde_starter.html

and a licence number is also

required for the software. This is all

free, if rather tedious.

Any of the dozens of available ver-

sions of the GAL16V8 can be used.

The suffixes simply indicate the max-

imum supply current and propaga-

tion delay (in ns). Suffix R has noth-

ing to do with the type number: it

indicates, in ABEL notation, that the

GAL is used in ‘registered’ (as

opposed to ‘complex’ or ‘simple’)

mode. In registered mode, the clock

input is always on pin 1 and output

enable (OE) is always on pin 11. OE

must be held low to enable the

device’s outputs. With other compil-

ers, the suffix codes may be different.

Software

The software consists of source code in

ABEL-HDL, in the ﬁle PULS.REP or — if you

would rather not get involved in ABEL code

— as a JEDEC ﬁle PULS.JED for direct pro-

gramming into the GAL. Both ﬁles are avail-

able on disk, order code 000123-11 or as a

free download from the Elektor Electronics

website www.elektor-electronics.co.uk .

PWM in practice

We now give some advice on using

the pulse width modulator in prac-

tice. The clock frequency must be 32

times higher than the desired output

switching frequency. For example, if

a DC motor is to be driven, a clock

frequency of at least 500 kHz is rec-

ommended. The resulting PWM fre-

quency of 15.6 kHz is high enough to

ensure that noise produced by the

motor as a result of being driven

with AC is of too high a frequency to be

heard. If a higher frequency is used, eddy cur-

rent losses will become too great and the

motor may become too warm.

(000123-1)

P16V8R Programmed Logic:

Q10 = !( !Q2.PIN & c

# Q2.PIN & !c

# !Q1.PIN & b

# Q1.PIN & !b

# !Q0.PIN & a

# Q0.PIN & !a );

Q11 = !( over

# !Q3.PIN & d

# Q3.PIN & !d

# !Q4.PIN & e

# c & b & a & d & e

# Q4.PIN & !e );

Q3.D = ( Q0.PIN & Q1.PIN & Q2.PIN & Q3.PIN

# !Q0.PIN & !Q3.PIN

# !Q1.PIN & !Q3.PIN

# !Q2.PIN & !Q3.PIN ); “ ISTYPE ‘INVERT’

Q3.C = ( CLK );

Q2.D = ( Q0.PIN & Q1.PIN & Q2.PIN

# !Q0.PIN & !Q2.PIN

# !Q1.PIN & !Q2.PIN ); “ ISTYPE ‘INVERT’

Q2.C = ( CLK );

Q1.D = ( Q0.PIN & Q1.PIN

# !Q0.PIN & !Q1.PIN ); “ ISTYPE ‘INVERT’

Q1.C = ( CLK );

Q0.D = ( Q0.PIN ); “ ISTYPE ‘INVERT’

Q0.C = ( CLK );

Q4.D = ( !Q4.PIN & !Q0.PIN

# !Q4.PIN & !Q1.PIN

# !Q4.PIN & !Q2.PIN

# Q4.PIN & Q0.PIN & Q1.PIN & Q2.PIN & Q3.PIN

# !Q4.PIN & !Q3.PIN ); “ ISTYPE ‘INVERT’

Q4.C = ( CLK );

Pulsbreit.D = ( Q11.PIN & Q10.PIN

# Q4.PIN & Pulsbreit.Q

# Q0.PIN & Pulsbreit.Q

# Q1.PIN & Pulsbreit.Q

# Q2.PIN & Pulsbreit.Q

# Q3.PIN & Pulsbreit.Q

# !over & !c & !b & !a & !d & !e & Pulsbreit.Q );

“ ISTYPE ‘INVERT’

Pulsbreit.C = ( CLK );

Notation: &= AND, ‚ = OR, ! = negation

Figure 2. The logic expressed in ABEL-HDL.

1/2001

Elektor Electronics

53

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