Ad9852.pdf

CMOS 300 MHz

Complete-DDS

AD9852

PRELIMINARY TECHNICAL DATA

Automatic Bi-directional Frequency Sweep

SIN (X)/X Correction

Simplified Control Interface:

10 MHz Serial, 2 or 3-wire SPI compatible or

100 MHz Parallel 8-Bit Byte Programming

+3.3 V Single Supply

Multiple Power-Down Functions

Single-Ended or Differential Input Reference Clock

Small 80 -pin LQFP Packaging

FEATURES

300 MHz Internal Clock Rate

12-bit Sine Wave Output DAC

12-bit Auxiliary or Control DAC

Ultra High-speed, 3ps RMS Jitter Comparator

Excellent Dynamic Performance:

80 dB SFDR @ 100 MHz ( – 1 MHz) Aout

4 · - 20 · Programmable Reference Clock Multiplier

Dual 48-bit Programmable Frequency Registers

Dual 14-bit Programmable Phase Offset Registers

12-bit Amplitude Modulation and Programmable Shaped

On-Off Keying Function

Single pin FSK and PSK data interface

Linear or Non-Linear FM Chirp Functions with Single

Pin Frequency “Hold” Function

Frequency-Ramped FSK

APPLICATIONS

Agile, L.O. Frequency Synthesis

Programmable Clock Generator

FM Chirp Source for Radar and Scanning Systems

Test and Measurement Equipment

Commercial & Amateur RF exciter

AD9852 Block Diagram

300 MHz

DDS

Digital Multiplier

Diff./Single

Select

Inv.

Sinc

Filter

12-Bit DDS

DAC

Analog Out

4X - 20X

Ref. Clock

Multiplier

Reference

Clock In

DAC R SET

Phase/Offset

Modulation

Ramp-up/Down

Clock/Logic &

Multiplexer

System

Clock

12-Bit Control

DAC

Analog Out

12-bit Data

FSK/BPSK/HOLD

Frequency Tuning Word/Phase Word

Multiplexer & Ramp Start Stop Logic

Data In

AD9852

Shaped

On-Off Keying

Amplitude

Modulation

Data

14-bit Phase

Offset/

Modulation

48-bit Frequency

Tuning Word

Bi-directional

I/O Update

Analog In

Programming Registers

Read

Comparator

Programmable Rate

and Update Clocks

I/O Port Buffers

Clock Out

Write

Master

Reset

Serial/Parallel

Select

+Vs

Gnd

8-bit Parallel

Load

6-bit Address

or Serial

Programming

lines

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog devices for its use, nor for any infringements of

patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

7/20/99 REV. PrA

AD9852 PRELIMINARY TECHNICAL DATA

_____________________________________________________________________________________________________

GENERAL DESCRIPTION

The AD9852 digital synthesizer is a highly integrated CMOS

device that uses advanced DDS technology, coupled with (2)

internal high-speed, high performance D/A converters and

comparator to form a digitally-programmable single-tone

frequency synthesizer. When referenced to an accurate clock

source, the AD9852 generates a highly stable, frequency, phase

and amplitude programmable sinewave output that can be used as

an agile L.O. in communications, radar, and many other

applications. The AD9852's innovative high-speed DDS core

provides 48-bit frequency resolution (1 microHertz tuning steps).

Phase truncation to 17-bits assures excellent digital SFDR

performance. The AD9852's circuit architecture allows the

generation of a single-tone output at frequencies up to 150 MHz,

which can be digitally tuned at a rate of up to 100 million new

frequencies per second. The (externally filtered) sine wave output

can be converted to a square wave using the internal comparator

for agile clock generator applications. The device provides 14-

bits of digitally-controlled phase modulation and single-pin PSK.

The 12-bit DAC, coupled with the innovative DDS architecture,

provide excellent wideband and narrowband analog output

SFDR. The 12-bit auxiliary DAC is user-programmable and can

accept input data at a 100 MSPS (maximum) rate. When

configured with the on-board comparator, the 12-bit control DAC

facilitates pulse-width modulation (PWM) and static duty cycle

control, in the high-speed clock generator application. A 12-bit

digital multiplier permits programmable amplitude modulation of

the sine wave output, shaped on-off keying and precise amplitude

control. The AD9852’s programmable 4 · - 20 · REFCLK

Multiplier circuit generates the 300 MHz (maximum) clock

internally from a lower frequency external reference clock. This

saves the user the expense and difficulty of implementing a 300

MHz clock source. Direct 300 MHz clocking is also

accommodated with either single-ended or differential inputs.

Single-pin conventional FSK and the enhanced spectral qualities

of “ramped” FSK are provided. The AD9852 uses advanced .35

micron CMOS technology to provide this high level of

functionality on a single +3.3 V supply.

The AD9852 is available in a space-saving 80-pin LQFP surface

mount package. It is pin-for-pin compatible with the AD9854

Quadrature DDS. It is specified to operate over the extended

industrial temperature range of -40° to +85°C.

Preliminary Pin Assignments

AVDD

PIN 1

IDENTIFIER

AGND

DAC Rset

DACBP

AD9852

AVDD

AGND

TOP VIEW

(Not to Scale)

80-PIN LQFP 14 x 14 x 1.4

DVDD

IOUT2

IOUT2B

DVDD

DGND

AVDD

IOUT1B

DGND

IOUT1

A2/IO RESET

A1/SDO

A0/SDIO

AGND

AVDD

VINN

VINP

AGND

I/O UD

7/20/99 REV. PrA

AD9852 PRELIMINARY TECHNICAL DATA

_____________________________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS 1

Maximum Junction Temp. ....................................+150° C

Storage Temperature ............................

-65° C to +165° C

Vs ............................................................

+4 V

Operating Temp. ..................................

-40° C to +85° C

Digital Inputs ................................

-0.7 V to +Vs

Lead Temp. (10 sec. soldering) ...........................

+300° C

Digital Output Current ...............................

5 mA

Maximum Clock Frequency…………………… TBD MHz

AD9852 PRELIMINARY ELECTRICAL SPECIFICATIONS (V S =+3.3 V – 5%, R SET =3.9 k W ,

External reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10 · ) unless otherwise noted.

____________________________________________________________________________________________________

Parameter

Temp

Test Level

AD9852

Min Typ Max

Units

REF CLOCK INPUT CHARACTERISTICS 2

Internal Clock Frequency Range

FULL

300

MHz

External REF Clock Frequency Range:

REFCLK Multiplier Enabled

FULL

MHz

REFCLK Multiplier Disabled

FULL

300

MHz

Duty Cycle

+25°C

Input Capacitance

+25°C

Input Impedance

+25°C

100

M W

Common-mode Voltage Range (Differential Mode)

+25°C

TBD

V IH (Single-ended Mode)

+25°C

TBD

V IL (Single-ended Mode)

+25°C

TBD

DAC STATIC OUTPUT CHARACTERISTICS (apply to

both DDS and Auxiliary DAC’s)

Output Update Speed

FULL

300

MSPS

Resolution

+25°C

Bits

Full-Scale Output Current

+25°C

Gain error

+25°C

-10

+10

%FS

Output Offset

+25°C

Differential Non-linearity

+25°C

lsb

Integral Non-linearity

+25°C

lsb

Output Impedance

+25°C

100

k W

Voltage Compliance Range

+25°C

-0.5

+1.0

DDS DAC DYNAMIC OUTPUT CHARACTERISTICS

Wideband SFDR:

1 to 20 MHz Aout

+25°C

TBD

dBC

20 to 40 MHz Aout

+25°C

TBD

dBC

40 to 60 MHz Aout

+25°C

TBD

dBC

60 to 80 MHz Aout

+25°C

TBD

dBC

80 to 100 MHz Aout

+25°C

TBD

dBC

100 to 120 MHz Aout

+25°C

TBD

dBC

Narrowband SFDR:

10 MHz Aout ( – 1 MHz)

+25°C

TBD

dBC

10 MHz Aout ( – 250 kHz)

+25°C

TBD

dBC

10 MHz Aout ( – 50 kHz)

+25°C

TBD

dBC

10 MHz Aout ( – 10 kHz)

+25°C

TBD

dBC

30 MHz Aout ( – 1 MHz)

+25°C

TBD

dBC

30 MHz Aout ( – 250 kHz)

+25°C

TBD

dBC

30 MHz Aout ( – 50 kHz)

+25°C

TBD

dBC

30 MHz Aout ( – 10 kHz)

+25°C

TBD

dBC

50 MHz Aout ( – 1 MHz)

+25°C

TBD

dBC

50 MHz Aout ( – 250 kHz)

+25°C

TBD

dBC

50 MHz Aout ( – 50 kHz)

+25°C

TBD

dBC

50 MHz Aout ( – 10 kHz)

+25°C

TBD

dBC

70 MHz Aout ( – 1 MHz)

+25°C

TBD

dBC

70 MHz Aout ( – 250 kHz)

+25°C

TBD

dBC

70 MHz Aout ( – 50 kHz)

+25°C

TBD

dBC

70 MHz Aout ( – 10 kHz)

+25°C

TBD

dBC

7/20/99 REV. PrA

AD9852 PRELIMINARY TECHNICAL DATA

_____________________________________________________________________________________________________

AD9852 PRELIMINARY ELECTRICAL SPECIFICATIONS (V S =+3.3 V – 5%, R SET =3.9 k W ,

External reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10 · ) unless otherwise noted.

Parameter

Temp

Test Level

AD9852

Units

Min

Typ

Max

DAC Narrowband SFDR continued:

90 MHz Aout ( – 1 MHz)

+25°C

TBD

dBC

90 MHz Aout ( – 250 kHz)

+25°C

TBD

dBC

90 MHz Aout ( – 50 kHz)

+25°C

TBD

dBC

90 MHz Aout ( – 10 kHz)

+25°C

TBD

dBC

110 MHz Aout ( – 1 MHz)

+25°C

TBD

dBC

110 MHz Aout ( – 250 kHz)

+25°C

TBD

dBC

110 MHz Aout ( – 50 kHz)

+25°C

TBD

dBC

11 0MHz Aout ( – 10 kHz)

+25°C

TBD

dBC

DDS DAC SIGNAL-TO-NOISE RATIO (calculated)

+25°C

TBD

DDS DAC Residual Phase Noise (Freq TBD)

1 kHz Offset

+25°C

TBD

dBc/Hz

10 kHz Offset

+25°C

TBD

dBc/Hz

100 kHz Offset

+25°C

TBD

dBc/Hz

Pipeline Delays

TBD

+25°C

TBD

SysClk Cycles

Phase Accumulator & DSP Algorithm

+25°C

TBD

SysClk Cycles

Inverse Sinc Filter

+25°C

TBD

SysClk Cycles

Digital Multiplier

+25°C

TBD

SysClk Cycles

MASTER RESET DURATION

+25°C

SysClk Cycles

DIGITAL (AM) MULTIPLIER DYNAMIC RANGE

+25°C

TBD

COMPARATOR INPUT CHARACTERISTICS

Input Capacitance

+25°C

Input Resistance

+25°C

500

k W

Input Current

+25°C

– 12

m A

Hysteresis

+25°C

Input Voltage Range

+25°C

V DD

COMPARATOR OUTPUT CHARACTERISTICS

Logic "1" voltage, high Z load

FULL

+2.7

Logic "0" voltage, high Z load

FULL

+0.4

Output Power, 50-ohm load, 100 MHz toggle rate

+25°C

dBm

Propagation Delay

+25°C

Output Duty Cycle Error 3

+25°C

– 5

Rise/Fall Time

+25°C

Toggle Rate, high Z load

+25°C

300

MHz

Toggle Rate, 50-ohm load

+25°C

400

MHz

Output Jitter 4

+25°C

ps RMS

COMPARATOR NARROWBAND SFDR 5

10 MHz ( – 1 MHz)

+25°C

TBD

dBC

10 MHz ( – 250 kHz)

+25°C

TBD

dBC

10 MHz ( – 50 kHz)

+25°C

TBD

dBC

10 MHz ( – 10 kHz)

+25°C

TBD

dBC

70 MHz ( – 1 MHz)

+25°C

TBD

dBC

70 MHz ( – 250 kHz)

+25°C

TBD

dBC

70 MHz ( – 50 kHz)

+25°C

TBD

dBC

70 MHz ( – 10 kHz)

+25°C

TBD

dBC

110 MHz ( – 1 MHz)

+25°C

TBD

dBC

110 MHz ( – 250 kHz)

+25°C

TBD

dBC

110 MHz ( – 50 kHz)

+25°C

TBD

dBC

110MHz ( – 10 kHz)

+25°C

TBD

dBC

“CLOCK GENERATOR” OUTPUT JITTER 5 @

5 MHz

+25°C

ps RMS

7/20/99 REV. PrA

AD9852 PRELIMINARY TECHNICAL DATA

_____________________________________________________________________________________________________

AD9852 PRELIMINARY ELECTRICAL SPECIFICATIONS (V S =+3.3 V – 5%, R SET =3.9 k W ,

External reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10 · ) unless otherwise noted.

10 MHz

+25°C

ps RMS

40 MHz

+25°C

ps RMS

80 MHz

+25°C

ps RMS

120 MHz

+25°C

ps RMS

CMOS LOGIC INPUTS

Logic "1" Voltage

+25°C

2.7

Logic "0" Voltage

+25°C

0.4

Logic "1" Current

+25°C

– 12

Logic "0" Current

+25°C

– 12

Input Capacitance

+25°C

POWER SUPPLY

+Vs Current 6

+25°C

1000

+Vs Current 7

+25°C

600

P Diss 6

+25°C

3.3

P Diss 7

+25°C

P DISS Power-down Mode

+25°C

NOTES

Comparator input originates from DDS section via

external 7-pole elliptic LPF. Single-ended input, .5V p-p.

Comparator output terminated 50 Ohms.

Absolute maximum ratings are limiting values, to be

applied individually, and beyond which the serviceability

of the circuit may be impaired. Functional operability

under any of these conditions is not necessarily implied.

Exposure of absolute maximum rating conditions for

extended periods of time may affect device reliability.

All functions engaged

All functions except inverse sinc and digital multipliers

engaged.

The reference clock inputs are configured to accept a 1 V

p-p (minimum) dc offset sine wave centered at ½ the

applied Vdd or a 3 V TTL-level pulse input.

EXPLANATION OF TEST LEVELS

Test Level

I - 100% Production Tested.

III - Sample Tested Only.

IV - Parameter is guaranteed by design and

characterization testing.

V - Parameter is a typical value only.

VI - All devices are 100% production tested at +25°C.

100% production tested at temperature extremes for

military temperature devices; guaranteed by design

and characterization testing for industrial devices.

Change in duty cycle from 1 to 100 MHz with 1V p-p

sine wave input and .5V threshold.

Represents comparator’s inherent jitter contribution.

Input signal is a 1 volt, 40 MHz square wave.

Measurement device Wavecrest DTS – 2075.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9852AST

AD9852ASQ

AD9852/PCB

7/20/99 REV. PrA

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