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Texas Instruments Incorporated

Power Management

Practical considerations when designing

a power supply with the TPS6211x

By Jeff Falin, Power Management Products/Portable Power dc/dcApplications (Email: j-falin1@ti.com),

and Bill Johns, Power Management Products/Portable Power dc/dcApplications (Email: w-johns2@ti.com)

The TPS6211x dc/dc converter is a synchro-

nous buck converter capable of input voltages

up to 17 V, output voltages from 1.2 to 16 V,

and output currents up to 1.5 A. The device

efficiently steps down 2-cell Li-ion or lead-

acid batteries, or 12- to 15-V system rails, to

5 V, 3.3 V, or lower. A typical application circuit

is shown in Figure 1.

This article provides an example application

and summarizes the key features of designing

with the TPS6211x buck converter.

External component sizing

Integrated FETs and internal compensation

reduce the required number of external parts

to very few. Assuming that the integrated

output-voltage and input-voltage supervisory

circuits are not used, the fixed-output-voltage

(5-V or 3.3-V) versions need only four components: an

input capacitor for the power switches, an input filter

capacitor for the analog input pin, an output capacitor

(C), and a power inductor (L). The device has been inter-

nally compensated to work with an L of 6.8 µH and a C of

at least 22 µF. Other values of L and C will provide satis-

factory operation, and increasing either or both values

will reduce output ripple. It is recommended that the LC

product remain close to the minimum of 6.8 µH

Figure 1. Typical application

6.8 µH

V IN = 3.8 V to 17 V

V OUT = 3.3 V

TPS62111

VIN

E VIN

1 M

Ω

VINA

1 µF

LBO

AGND

C IN = 10 µF

25 V

LBI

C OUT = 22 µF

6.3 V

SYNC

GND

GND P W PD PGND PGND

IC’s high-voltage PMOS FET has plenty of gate drive to

provide ±3% regulation from no load to 1.5 A. At lower

input voltages, the IC still provides ±3% regulation from

no load up to 1.2 A for 6 V > V IN > 4.3 V; 500 mA for 4.3 V

> V IN > 3.5 V; and 300 mA for 3.5 V > V IN > 3.1 V. Using a

high-side PMOS FET allows 100% duty-cycle operation,

during which time the output is tied directly to a nearly

depleted battery to maximize battery life.

Assuming that the recommended output-filter product is

used, the device is compensated to provide excellent load-

transient performance. Therefore, fast changes in output

load do not result in significant output-voltage droop

before the control loop responds. As shown in Figure 2,

the output voltage droops less than 100 mV during a 1-A

22 µF

for stability. Two additional feedback resistors and a feed-

forward capacitor are required for the adjustable version,

which provides output voltages from 1.2 to 16 V. The out-

put voltage supervisory circuit (called power good, or PG,

output) provides a logic high when the output is above

approximately 98.6% of its nominal voltage. The low-

battery indicator is a stand-alone supervisory circuit, active

only after EN is pulled high, with a low-battery input (LBI)

that is intended to monitor battery input voltage and a

low-battery output (LBO) that provides a logic low when

the input voltage drops below a certain voltage. LBI

requires two external feedback resistors to set the trip

point and, if not used, should be pulled low as shown in

Figure 1. Both PG and LBO are open-drain outputs pro-

viding for maximum user flexibility and therefore require

pull-up resistors if used but can be left floating if not used.

Output voltage regulation versus output current

The device’s proprietary control architecture ensures that

the output voltage maintains ±3% output voltage regula-

tion (excluding feedback resistor tolerances) across input

line and output load changes. For 17 V > V IN > 6 V, the

Figure 2. The 1-A load transient going from 12 to

3.3 V when L = 6.8 µH and C = 22 µF

1.5 A

I OUT (500 mA/div)

100 mA

V OUT (50 mV/div)

Time = 10 µs/div

Analog Applications Journal

1Q 2006

www.ti.com/aaj

High-Performance Analog Products

Power Management

Texas Instruments Incorporated

load transient (in forced pulse-width modulation [PWM]

mode) with a small 22-µF output capacitor. A larger out-

put capacitor reduces the droop even further.

PWM versus power-save mode

Efficiency varies inversely with the input to output voltage

differential for all converters. In addition, efficiency drops

dramatically at light loads for fixed-frequency PWM con-

verters due to the IC’s quiescent current and switching

losses dominating the output power being provided. To

improve efficiency at light load, the TPS6211x has a pulse-

frequency modulation (PFM), or power-save, mode that is

enabled by tying the SYNC pin low. Efficiency curves for

V OUT = 3.3 V and for various input voltages with power-

save mode enabled are shown in Figure 3.

a frequency between 800 kHz and 1.4 MHz. In addition,

since the synchronous FET allows current to flow back to

the input, there is always current flowing though the

inductor, keeping it in continuous conduction mode over

the entire load range. This eliminates the ringing that

occurs at the switch node after other converters enter

discontinuous mode. Therefore, at the expense of slightly

lower efficiency at light load, forcing the TPS6211x into

PWM mode provides extremely low-noise operation.

Output power

The TPS6211x’s 4-mm × 4-mm QFN package with

PowerPAD™ has a junction-to-pad thermal resistance

(R ΘJP ) of 8°C/W and a junction-to-ambient thermal resist-

ance (R

ΘJA ) of approximately 40°C/W for a high-K board

with no air flow. With power dissipation computed as

P Dmax = (T Jmax –T A )/R

ΘJA , maximum output power is com-

puted as P OUTmax = P Dmax /(1/η – 1), where T Jmax = 125°C

and

Figure 3. Efficiency of 3.3-V fixed-output version

of TPS62111 with power-save mode enabled

is the expected efficiency. For example, with typical

efficiencies of 85% and 89% at I OUT = 1.5 A, the 3.3- and

5-V fixed-output versions can easily provide 4.95 and 7.5 W,

respectively, from a 12-V input rail at 85°C ambient

temperature.

Typical applications

The TPS6211x family of buck converters is ideally suited

for a wide range of applications. For example, in the com-

puting world, the converter’s fast transient response is

useful for stepping down 12-V input rails to the 5- or 3.3-V

(or lower) rails that power fast-switching digital ICs in a

server/workstation or in a personal printer. Consumer

applications such as set-top boxes, which typically have

12-V ac/dc power supplies, and portable DVD players, with

either 9-V/12-V wall adapters or dual Li-ion (8.4-V nominal)

input power, have traditionally needed their input rails

stepped down to a 5- and/or 3.3-V midrange bus voltage

for I/O power. Further down-conversion of these bus volt-

ages by additional dc/dc switchers and/or linear regulators

to power the lower-voltage ICs in the box is also required.

However, with its high-efficiency, low-noise operation and

low minimum duty cycle, the TPS6211x can power the

lower-voltage (e.g., 2.5-V, 1.x-V) processors and peripher-

als directly, thereby eliminating the midrange bus and

improving efficiency and battery life, if applicable. Since

12- and 15-V rails are common in industrial applications,

this converter, with its low-noise mode and synchroniza-

tion feature, could be useful as a point-of-load regulator

powering a data acquisition system. Lastly, 2-cell Li-ion

and lead-acid battery-powered systems such as battery-

backup or alarm systems use the LBI/LBO feature, high

efficiency, and 100% duty cycle mode to provide maxi-

mum operation time by extending battery life.

Related Web sites

power.ti.com

www.ti.com/sc/device/TPS62111

100

4.2 V

5 V

8.4 V

12 V

V OUT = 3.3 V

T A = 25ºC

PFM Mode

0.0001

0.001

0.01

0.1

Output Current, I OUT (A)

In power-save mode, the TPS6211x’s quiescent current

is reduced, and the switches turn on only long enough to

keep the output voltage in regulation for a given load

current. This type of operation causes the output-voltage

ripple to be slightly higher (up to 1% of the output volt-

age) and to vary in frequency until being transitioned back

to fixed-frequency PWM mode at currents above approxi-

mately 280 mA for V IN > 7 V. In power-save mode there is

no minimum duty cycle. Low r DS(ON) FETs with copper

overlay reduce I 2 R losses and keep efficiency high at

heavy load as well.

The TPS6211x can be forced into fixed-frequency PWM

mode, resulting in extremely low-amplitude, fixed-frequency

output ripple (typically < 10 mV PP ) across the entire load

range, either by pulling SYNC high to V IN or by tying it to an

external oscillator. Pulling SYNC high results in the 1-MHz,

fixed-frequency operation. The device can be synchro-

nized through the SYNC pin to an external oscillator with

Analog Applications Journal

High-Performance Analog Products

www.ti.com/aaj

1Q 2006

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