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(EECtechnical.doc .. 11.20.97)
Technical Notes on The EEC-IV MCU
Compiled by Tom Cloud <cloud@peaches.ph.utexas.edu>
(all fonts are Courier New)
(The information supplied here was gotten through researching e-mail correspondence,
technical publications and from information given to the author. If it helps you, great!
If you learn more about the EEC, please return the favor by sharing what you learn with
me and others.)
If you were a contributor and didn't get acknowledged, flame me and I'll get it right in
the "next" edition. There were many contributors who didn't want me to remember them, so
I chose to delete most original corresponcences, hence the high probability that I may
have failed to acknowledge someone who wanted to be given credit.
DISCLAIMER: Beware -- none of this data is guaranteed to be accurate! Use it at your
own risk and please let me know what you learn so that I can add to and correct this.
CONTENTS:
INTRODUCTION
THE MCU/ECU
THE MICROPROCESSOR
CPU, ROM, RAM PINOUT
8061 MEMORY MAP
8061 INSTRUCTION SET
MCU PARTS LIST
ECM TEST PORT (J3) PINOUT
ECM CABLE PINOUT
EEC DIAGNOSTICS
EEC FUEL CONTROL
EEC IGNITION and TIMING CONTROL
EEC FUNCTIONS
EEC SCALARS
EEC TABLES
MAF CONVERSION
TERMS
EEC APPLICATIONS
EEC-IV REFERENCE SOURCES
AFTERMARKET SUPPLIERS
INTRODUCTION
I've collected and compiled data to help you decipher the EEC-IV inner workings.
Software algorithms and automotive control techniques are purposely absent as
the
EEC hardware and chip set are what I'm primarily interested in figuring out.
The EEC MCU probably controls one or more vehicles you own plus it contains all
the components necessary to build an efi system for any vehicle -- if only we
could program and modify it. That is my purpose -- to uncloak the EEC-IV so
that we can play with what we bought!
The sections titled EEC DIAGNOSTICS, FUEL CONTROL, IGNITION & TIMING CONTROL,
FUNCTIONS, SCALARS AND TABLES are departures from the goals stated above -- but
I felt it was informative and hated to discard it. If this were a formal
document, I would probably either ditch those sections, re-structure the
document's purpose to include them or write a separate document on control
algorithms.
1
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THE MCU
The EEC-IV was introduced in 1983 and has gone through several major physical
changes, with the earliest models showing a fairly simple two board design using
through hole soldered components. The last of the EEC-IV designs were much more
current in technology, showing extensive use of surface mount components and a
much more finished and complex appearance. In between, there appears to be a
variety of mother/daughter board and other designs. Still, they are all called
EEC-IV, although somewhere in its life there was a Ford P/N generational change.
Roy <spectric@globalnet.co.uk> writes: "The processor used is the 8065 along
with several supporting peripheral chips like the DUCE chip which can provide up
to 8 PWM outputs and the DARC chip which has 6 channels of timer capture
inputs." (Is he talking about the EEC-V here ?)
"This control unit is more suited to a history class than modern engine
management systems. All of the functions within the EEC, apart from the actual
power drivers, are now found within the micro controller such as the 68332 and
336."
The EEC module is rated to 80C (185F) continuous, 100C intermittent, so it will
be much happier and live longer in the passenger compartment. Some of the later
generation 15 and 18 MHz Motorola 8061 processors have a bus loading/edge timing
sensitivity that only gets worse at high temperature, so it's best to keep the
EEC in a more hospitable environment. Additionally, mounting the EEC in the
passenger compartment will give you better access to the J3 test port, which is
where you'll be plugging in a chip and/or the Calibrator.
The J3 test port on the side of the ECU box is for developers to plug into --
this is how the after-market chipmakers and others get into the box. The test
connector has the micro-controller's multiplexed address/data bus signals on it.
It also, very conveniently, has a PROM disable signal. So the chip makers
design something that hangs off that connector, disables the computer's PROM,
and substitutes its own PROM in its place.
2
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THE MICROPROCESSOR:
The micro-controller is an Intel 8061, a close cousin to the Intel 8096. It is
supplied by three manufacturers: Intel, Toshiba (6127) and Motorola, though the
Motorola units
seem to slip spec
a little and
differ in their
timing slightly
from the others.
There are some
major differences
between the 8061
and 8096 (e.g.
pinouts, bus
layout, etc.),
but most of the
code is
transferable.
XTAL
CONTROL PROCESSOR
MBUS
MB0-MB7
INSTRUCTION
REGISTER
M B
B U
U F
S F
C
L
&
I
O
N
R
E
OPCODE
ADDR
A-BUS 8
ANALOG
INPUTS
ADDR/
DATA
ADDR
DATA
ADDR
O
C
C
S
HI SPEED
INPUTS
REGISTER
FILE
(120 X 16)
INTERRUPT
CONTROLLER,
WATCHDOG
TIMER, I/O
STATUS
REGISTER
RALU
HI SPEED
OUTPUTS
The 8061 is an
8096 with a few
extra
instructions
added. One is a
very powerful
conditional jump
to complement the
high speed I/O
units. This
instruction, the
jump on bit equals zero, is used to test any one of the eight bits of a given
byte and jump if the bit equals zero (is this the JBC/JNB command?). Other
conditional jumps were added to aviod extensive data shifts. With a 15 MHz
input frequency, the 8061 can perform a 16-bit addition in 0.8 microseconds and
a 16 x 16 bit
multiply or a 32/16
bit divide in 5.2
microseconds (using
the hardware
multiply and divide
feature). For
typical
applications, based
on a normal
instruction mix,
instruction
execution times
average 1 to 2
microseconds. It
seems to have the
same functional pins
as the 8096, but
it's in a custom
package, so the
pinout is different.
Most of the signals
should be able to be
found with a scope
or logic analyzer.
The 8096 has a
PROGRAM
COUNTER
STACK
POINTER
LO SPEED
OUTPUTS
DATA
D-BUS (16)
DATA DATA
BIDIRECT
I/O 6
B
F
F
DATA
8
LSBs
8061
MICROPROCESSOR
ENABLE
RP0
READ
ONLY
PORT
I
O
RP5
SLAVE
PROGRAM
COUNTER
8
A
T
I
T
S
A
D
R
S
S
READ-ONLY
MEMORY
(16K X 16)
8
16
X
8
DATA
ADDRESS
REGISTER
8
16
ADDR
B
I U
N F
F
B
O U
U F
T F
DATA
MACHINE
STATE LOGIC
TRI-
STATE
CONTROL
SIGNALS
8763 EPROM
MBUS
MB0-MB7
3
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multiplexed address/data bus. The address/data bus signals are on the service
port connector (J3) along with a few others, possibly including the address
latch enable, read strobe, write strobe, and EPROM disable.
There are at
least two
hardware versions
of the 8061 chip.
One is a 40 pin
DIP and the other
is a square LCC
68 pin package.
The 68 pin
version has more
I/O and perhaps
other functions.
DATA
ENABLE
SLAVE
PROGRAM
COUNTER
N
S
Y
8
16
A
A
8
C
S
A
D
R
E
S
S
5
I/O-0
RANDOM-ACCESS
MEMORY
(1K X 16)
I
/
O
EXECUTE
ENABLE
REGISTER
16
I/O
PORT
I/O-4
U
T
U
X
8
A
A
5
The
address/multiplex
ing scheme is
similar to that
of the 8085 which
has AD0 .. AD7
and then A8 ..
A15 so the 8085
"latches" the
address
information A7:0,
and maintains
A8:15 while it is
using AD0 .. AD7
as D7:0 ....
DATA
ADDRESS
REGISTER
8
16
B
I U
N F
F
B
O U
U F
T F
ADDR/DATA
DATA
MACHINE
STATE LOGIC
TRI-
STATE
CONTROL
SIGNALS
MBUS
MB0-MB7
81C61 RAM - I/O
On the 8061 there are ONLY AD0 .. AD7 none of the "other" address lines so ...
when the 8061 wants to read an address it must
1) present 8 bits of the address and send the latch signal
2) present the OTHER 8 bits of the address and send the latch
3) enable the "Read Enable" flag, and read the 8 data bits
LEGEND
ADDR
ADDRESS
I/O
INPUT/OUTPUT
ASSY
ASSEMBLY
LO
LOW
A-BUS
ADDRESS BUS
LSB
LEAST SIGNIFICANT BIT
BIDIRECT BIDIRECTIONAL
MBus
MEMORY BUS
BUFF
BUFFER
EPROM
ERASABLE READ-ONLY MEMORY
CTRL
CONTROL
MUX
MULTIPLEXER
D-BUS
DATA BUS
RAM
RANDOM ACCESS MEMORY
HI
HIGH
RPn
READ-ONLY PORT INPUT
CPU, ROM, RAM PINOUT
8061 CPU (IC-1)
1
35
GND
2
36
Vss+
3
37
4
38
5
39
4
11/20/97
6
40
7
41
8
42
9
43
10
44
MB0
11
Vcc
45
MB1
12
46
MB2
13
47
MB3
14
48
MB4
15
49
MB5
16
50
MB6
17
51
MB7
18
GND
52
19
53
20
TP analog in
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
MAP f-v
66
xtal
33
67
xtal
34
68
87C61 RAM/IO (IC-7)
1
13
CPU-65, J3-13
MB3
2
/OE
14
CPU-64, J3-11
MB4
3
15
CPU-63, J3-9
MB5
4
GND (?)
16
CPU-62, J3-7
MB6
5
17
CPU-61, J3-5
MB7
6
GND (?)
18
7
19
GND (?)
8
20
address bit
9
21
address bit
10
CPU-68, J3-19
MB0
22
address bit
11
CPU-67, J3-17
MB1
23
12
CPU-66, J3-15 MB2 24 GND
CPU is IC-1, J3 is service connector
8763 EPROM (IC-8)
1
J3-22, 1K to +5V
13
CPU-65, J3-13
MB3
2
J3-16, 10K to +5
14
CPU-64, J3-11
MB4
3
15
CPU-63, J3-9
MB5
4
GND
16
CPU-62, J3-7
MB6
5
17
CPU-61, J3-5
MB7
6
18
+5V
7
+5
19
+5V
8
GND
20
CPU-59, J3-21
9
J3-12
21
CPU-58, J3-23
5
11/20/97
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