intel_arch_optimization.pdf

Intel ® Architecture

Optimization

Reference Manual

Issued in U.S.A.

Order Number: 245127-001

Intel ® Architecture

Optimization

Reference Manual

Order Number: 730795-001

Revision

Revision History

Date

001

Documents Streaming SIMD Extensions optimization

techniques for Pentium ® II and Pentium III processors.

02/99

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel

or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Con-

ditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied war-

ranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular

purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are

not intended for use in medical, life saving, or life sustaining applications.

This Intel® Architecture Optimization manual as well as the software described in it is furnished under license and may

only be used or copied in accordance with the terms of the license. The information in this manual is furnished for infor-

mational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corpora-

tion. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this

document or any software that may be provided in association with this document.

Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or trans-

mitted in any form or by any means without the express written consent of Intel Corporation.

Intel may make changes to specifications and product descriptions at any time, without notice.

* Third-party brands and names are the property of their respective owners.

Contents

Introduction

Tuning Your Application ......................................................... xvii

About This Manual................................................................ xviii

Related Documentation .......................................................... xix

Notational Conventions............................................................ xx

Chapter 1

Processor Architecture Overview

The Processors’ Execution Architecture................................ 1-1

The Pentium ® II and Pentium III Processors Pipeline....... 1-2

The In-order Issue Front End ....................................... 1-2

The Out-of-order Core.................................................. 1-3

In-Order Retirement Unit .............................................. 1-3

Front-End Pipeline Detail .................................................. 1-4

Instruction Prefetcher ................................................... 1-4

Decoders ...................................................................... 1-4

Branch Prediction Overview ......................................... 1-5

Dynamic Prediction ...................................................... 1-6

Static Prediction ........................................................... 1-6

Execution Core Detail ....................................................... 1-7

Execution Units and Ports ............................................ 1-9

Caches of the Pentium II and Pentium III

Processors ............................................................... 1-10

Store Buffers .............................................................. 1-11

iii

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