74HC164.pdf

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February 2008
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
Features
General Description
High Speed: f
=
175MHz at V
=
5V
The VHC164 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHC164 is a high-speed 8-Bit
Serial-In/Parallel-Out Shift Register. Serial data is
entered through a 2-input AND gate synchronous with
the LOW-to-HIGH transition of the clock. The device fea-
tures an asynchronous Master Reset which clears the
register, setting all outputs LOW independent of the
clock. An input protection circuit insures that 0V to 7V
can be applied to the input pins without regard to the
supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
■
MAX
CC
Low power dissipation: I
=
4µA (max.) at T
=
25°C
■
CC
A
High noise immunity: V
=
V
=
28% V
(min.)
■
NIH
NIL
CC
Power down protection provided on all inputs
■
Low noise: V
=
0.8V (max.)
■
OLP
Pin and function compatible with 74HC164
■
Ordering Information
Package
Number
Order Number
Package Description
74VHC164M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74VHC164SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC164MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74VHC164N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC164 Rev. 1.4.0
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Connection Diagram
Logic Symbol
Function Table
Pin Description
Operating
Mode
Inputs
Outputs
Pin
Names
Description
MR
ABQ
Q
–Q
0
1
7
Reset (Clear)
L
X
X
L
L–L
A, B
Data Inputs
Shift
H
L
L
L
Q
–Q
0
6
CP
Clock Pulse Input (Active Rising Edge)
HLHL Q
–Q
0
6
MR
Master Reset Input (Active LOW)
HHL L Q
–Q
0
6
Q
–Q
Outputs
0
7
HHHH Q
–Q
0
6
H
=
HIGH Voltage Levels
Functional Description
L
=
LOW Voltage Levels
X
=
Immaterial
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
Q
Lower case letters indicate the state of the
referenced input or output one setup time prior to
the LOW-to-HIGH clock transition.
=
the
logical AND of the two data inputs (A • B) that existed
before t he rising clock edge. A LOW level on the Master
Reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all Q outputs LOW.
0
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC164 Rev. 1.4.0
2
863383189.009.png 863383189.010.png 863383189.011.png
 
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5V to +7.0V
CC
V
DC Input Voltage
–0.5V to +7.0V
IN
V
DC Output Voltage
–0.5V to V
+ 0.5V
OUT
CC
I
Input Diode Current
–20mA
IK
I
Output Diode Current
±20mA
OK
I
DC Output Current
±25mA
OUT
I
DC V
/ GND Current
±75mA
CC
CC
T
Storage Temperature
–65°C to +150°C
STG
T
Lead Temperature (Soldering, 10 seconds)
260°C
L
(1)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
2.0V to 5.5V
CC
V
Input Voltage
0V to +5.5V
IN
V
Output Voltage
0V to V
OUT
CC
T
Operating Temperature
–40°C to +85°C
OPR
t
, t
Input Rise and Fall Time,
V
r
f
=
3.3V ± 0.3V
0ns/V
∼
100ns/V
CC
V
=
5.0V ± 0.5V
0ns/V
∼
20ns/V
CC
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC164 Rev. 1.4.0
3
863383189.012.png
DC Electrical Characteristics
T
=
–40°C to
+85°C
A
T
=
25°C
A
Symbol
Parameter
V
(V)
Conditions
Min.
Typ.
Max.
Min.
Max.
Units
CC
V
HIGH Level Input
Voltage
2.0
1.50
1.50
V
IH
3.0–5.5
0.7 x V
0.7 x V
CC
CC
V
LOW Level Input
Voltage
2.0
0.50
0.50
V
IL
3.0–5.5
0.3 x V
0.3 x V
CC
CC
V
HIGH Level
Output Voltage
2.0
V
=
V
I
=
–50µA
1.9
2.0
1.9
V
OH
IN
IH
OH
or V
IL
3.0
2.9
3.0
2.9
4.5
4.4
4.5
4.4
3.0
I
=
–4mA
2.58
2.48
OH
4.5
I
=
–8mA
3.94
3.80
OH
V
LOW Level
Output Voltage
2.0
V
=
V
I
=
50µA
0.0
0.1
0.1
V
OL
IN
IH
OL
or V
IL
3.0
0.0
0.1
0.1
4.5
0.0
0.1
0.1
3.0
I
=
4mA
0.36
0.44
OL
4.5
I
=
8mA
0.36
0.44
OL
I
Input Leakage
Current
0–5.5
V
=
5.5V or GND
±0.1
±1.0
µA
IN
IN
I
Quiescent
Supply Current
5.5
V
=
V
or GND
4.0
40.0
µA
CC
IN
CC
Noise Characteristics
T
25°C
=
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Limits
Units
CC
OLP (2)
V
Quiet Output Maximum
Dynamic V
5.0
C
=
50pF
0.5
0.8
V
L
OL
OLV (2)
V
Quiet Output Minimum
Dynamic V
5.0
C
=
50pF
–0.5
–0.8
V
L
OL
IHD (2)
V
Minimum HIGH Level
Dynamic Input Voltage
5.0
C L = 50pF
3.5
V
V ILD (2)
Maximum LOW Level
Dynamic Input Voltage
5.0
C L = 50pF
1.5
V
Note:
2. Parameter guaranteed by design.
©1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC164 Rev. 1.4.0
4
863383189.013.png
AC Electrical Characteristics
T A
–40°C
to +85°C
=
T A
25°C
=
Symbol
Parameter
V CC (V)
Conditions
Min.
Typ.
Max.
Min.
Max.
Units
f MAX
Maximum Clock
Frequency
3.3 ± 0.3
C L = 15pF, R L = 1k Ω
80
125
65
MHz
C L = 50pF, R L = 1k Ω
50
75
45
5.0 ± 0.5
C L = 15pF, R L = 1k Ω
125
175
105
C L = 50pF, R L = 1k Ω
85
115
75
t PLH , t PHL
Propagation Delay
Time (CP–Q n )
3.3 ± 0.3
C L = 15pF, R L = 1k Ω
8.4
12.8
1.0
15.0
ns
C L = 50pF, R L = 1k Ω
10.9
16.3
1.0
18.5
5.0 ± 0.5
C L = 15pF, R L = 1k Ω
5.8
9.0
1.0
10.5
C L = 50pF, R L = 1k Ω
7.3
11.0
1.0
12.5
t PHL
Propa gati on Delay
Time (MR–Q n )
3.3 ± 0.3
C L = 15pF, R L = 1k Ω
8.3
12.8
1.0
15.0
ns
C L = 50pF, R L = 1k Ω
10.8
16.3
1.0
18.5
5.0 ± 0.5
C L = 15pF, R L = 1k Ω
5.2
8.6
1.0
10.0
C L = 50pF, R L = 1k Ω
6.7
10.6
1.0
12.0
C IN
Input Capacitance
V CC = Open
4
10
10
pF
(3)
C PD
Power Dissipation
Capacitance
76
pF
Note:
3. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I CC (opr.) = C PD • V CC • f IN + I CC .
AC Operating Requirements
T A
–40°C
to +85°C
=
T A
25°C
=
V CC (V) (4)
Guaranteed
Minimum
Symbol
Parameter
Typ.
Units
t W (L), t W (H)
Minimum Pulse Width (CP)
3.3
5.0
5.0
ns
5.0
5.0
5.0
t W (L)
Minimum Pulse Width (MR)
3.3
5.0
5.0
ns
5.0
5.0
5.0
t S
Minimum Setup Time
3.3
5.0
6.0
ns
5.0
4.5
4.5
t H
Minimum Hold Time
3.3
0.0
0.0
ns
5.0
1.0
1.0
t REC
Minimum Removal Time (MR)
3.3
2.5
2.5
ns
5.0
2.5
2.5
Note:
4. V CC is 3.3 ± 0.3V or 5.0 ± 0.5V
©1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC164 Rev. 1.4.0
5
863383189.014.png
 

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